The CAMIF, also the Camera Interface block is the hardware block that interfaces with different image sensor interfaces and provides a standard output that can be used for subsequent image processing.
A typical Camera Interface would support at least a parallel interface although these days many camera interfaces are beginning to support the MIPI CSI interface.
The camera interface's parallel interface consists of the following lines :-
8 to 12 bits parallel data line
Horizontal Sync (HSYNC)
Vertical Sync (VSYNC)
Pixel Clock (PCLK)
NOTE: The above lines are all treated as input lines to the Camera Interface hardware.
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Example
Let us suppose that a sensor is transmitting a VGA frame 640x480. The video frame is of a format RGB888. Let's assume that we have a camera sensor transmitting 8 bits per pixel clock (PCLK). This means to transfer one pixel of data, 3 PCLKs would be required. The HSYNC would be fired by the sensor after every 640 x 3, 1920 PCLKs. A VSYNC would be fired by the sensor after the entire frame is transmitted i.e. after 1920x480, 921600 PCLKs.
The camera interface's hardware block (that could be a part of any SOC) would constantly monitor the above lines to see if the sensor has transmitted anything. A typical camera interface would come with some internal buffering and would also have an associated DMA to transfer the image to the destination memory. The buffer would capture the incoming pixels to temporarily buffer them, and using the DMA the pixels would be transferred (probably line by line) through multiple burst DMA transfers to a destination address in the memory (pre programmed by the camera interface driver programmer). The camera interface's programmer interface might also give a facility of issuing hardware interrupts upon the receipt of the HSYNC, VSYNC signals to the host micro-controller. This could serve as a useful trigger for DMA reprogramming if required.
Camera Clocks Video
Hardware vendors
Many single-board computers, such as the Raspberry Pi, the Orange Pi PC or the Cubieboard contain a MIPI CSI connector.
Source of the article : Wikipedia
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